Even on the desktop processors, there are onboard lanes dedicated to the NVMe itself, and the entire processor (including NVMe) is capable of booting without a supporting chipset at all - the "X300 chipset" is actually not a chipset at all, it is just using the SOC itself without an external chipset, and you do not lose NVMe functionality.
Not sure if you are using some really weird meaning of "NVMe controller" that doesn't match what anyone else means?
I meant the controller that manages the NAND cells, I assumed it would be called NVMe controller. Essentially the IC that the "NVMe controller" in your image talks to.
That would normally be called a "flash controller" and yeah, of course that lives on the SSD.
(unless it doesn't - eMMC doesn't normally have a flash controller and you just do direct writes to the flash cells... as do some IOFusion PCIe cards that are just flash directly attached to PCIe with no controller. Sometimes that functionality is just software-based. Flash cards (eg microSD) usually also do not have a flash controller directly either.)
Anyway, it's true though that Apple does push the flash controller functionality into the SOC while AMD does not, Apple implements their SSD in a non-standard fashion, that's why it's not compatible with off-the-shelf drives. The flash is just flash on a board, I don't even think it's NVMe compatible at all either.
So if you want to be maximally pedantic... neither does Apple implement onboard NVMe controllers, just flash controllers ;)
FYI, all current flash card formats have the equivalent of an SSD controller, implementing a Flash Translation Layer. Exposing raw NAND was somewhat viable in the very early days when everything was using large SLC memory cells (see SmartMedia and xD-Picture Card), but no current format could remain usable for long without wear leveling. If you can use standard filesystems and access the drive or card from multiple operating systems, then it must be providing its own FTL rather than relying on the host software for wear leveling.
The above also applies to eMMC and UFS storage as found in devices like smartphones.
AMD processors provide PCIe lanes, some of which are intended for use with NVMe SSDs but nothing on the chip actually implements or understands NVMe and the lanes used for the SSD in a typical system design are still fully generic PCIe lanes.
> nothing on the chip actually implements or understands NVMe
pretty sure that's false as well... can an X300 system boot a NVMe drive? I'd assume yes. It does that with a UEFI which lives... where? Oh right, on the chip.
Most NVMe SSDs don't provide legacy option roms anymore either.
> It does that with a UEFI which lives... where? Oh right, on the chip.
No, UEFI is firmware stored on a flash chip on the motherboard, usually connected to the CPU through the LPC bus. CPUs do not have any nonvolatile storage onboard (unless you count eFuses).
